10.1 MEMORY/HARDWARE CONFIGURATION
MCS BASIC-52 always requires at least 1K bytes of external memory. After reset, MCS BASIC-52 sizes the external memory. If less than 1K bytes of external memory are available, MCS BASIC-52 will not "sign-on." in fact, it will internally loop forever. This obviously is not too exciting, so it is wise to hang some extemal memory on the MCS BASIC-52 device.
MCS BASIC-52 sizes consecutative external memory locations from 0000H until a memory failure is detected. The sizing operation is performed simply by writing a 5AH to an external memory location, then testing the location. If the particular memory location passes this test, BASIC then writes a 00H to the location, then again, checks the location. MCS BASIC-52 only sizes the external memory from locations 0 through 0DFFFH. Memory locations 0E000H through 0FFFFH are reserved for user I/O and/or assembly language programs.
The MCS BASIC-52 program resides in the 8K of ROM available in INTEL's 8052AH device and as a result requires that external memory be "partitioned" in a specific manner. The architecture of the 8052AH is NOT Von Neumann. This means that Data and Program Memory do not reside in the same physical address space on the 8052AH. Specifically, the /RD (pin 17) and /WR (pin 16) pins on the 8052AH are used to enable DATA memory and /PSEN (pin 29) pin is used to enable PROGRAM memory. Depending on the hardware configuration, MCS BASIC-52 operates in two distinct "memory" modes.
RAM ONLY MODE
In this mode of operation, Read/write memory is connected to the MCS BASIC-52 device starting at memory address 0000H. Memory can be placed up to location 0FFFFH. In this mode of operation the decoded addresses are used to generate the CHIP SELECT (/CS) signal for the RAM devices. The RD pin on the 8052AH is used to generate the OUTPUT ENABLE (/OE) strobe and the /WR pin generates the WRITE ENABLE (/WE or /WR) strobe. /PSEN is not used in the RAM only mode of operation. The RAM only mode of operation offers the simplest hardware configuration available for the MCS BASIC-52 device. An example of this configuration is shown in Figure 1. Since /PSEN is not used in the RAM only mode, the user may not CALL assembly language routines. The RAM only also does not support EPROM programming. In general, the RAM only mode will be used only to "check out" the device during the initial system development stage.
The RAM/EPROM mode of operation allows for the complete system implementation of MCS BASIC-52. This mode of operation requires that external memory be mapped in a certain manner. The RAM/EPROM memory configuration is as follows:
I) The /RD and the &WR pins on the MCS BASlC-52 device are used to enable RAM memory that is addressed from 0000H to 7FFFH. Addresses are used to decode the chip select (/CS) for the RAM devices and /RD and /WR are used to enable the /OE and /WE or (/WR) pins respectively.
2) The /PSEN pin on the MCS BASIC-52 device is used to enable EPROM memory that is addressed from 2000H to 7FFFH. Addresses are used to decode the chip select (/CS) for the EPROM devices and /PSEN is used to enable the /OE pin.
3) For addresses between 8000H and 0FFFFH both the /RD and the /PSEN pin on the MCS BASIC-52 device are used to enable the memory. Either EPROM or RAM devices can be placed in this address space. To permit both the /RD and the /PSEN pins to enable addresses in this address space, /RD and /PSEN must be logically "ANDED" together. This can be accomplished with a simple TTL gate such as a 74LS08. The /WR pin on the MCS BASIC-52 device is used to write to RAM memory in this same address space. The /PSEN and /RD signals do not have to be anded beyond address 7FFFH to enable MCS BASIC-52 to program an EPROM. This is only a suggestion since it will permit the user to execute assembly language routines as well as MCS BASIC-52 programs that are located in this address space.
This scheme of memory addressing actually permits MCS BASIC-52 to address 96K bytes of memory, 32K of RAM devices, 32K of EPROM/ROM devices and 32K of combined RAM/EPROM/ROM devices. Since /RD and /PSEN are ANDED for addresses from 8000H through 0FFFFH, the 8052AH "looks like" a Von Neumann machine in this address space. The XBY and CBY special function operators will yield the same value when their arguments are between 8000H and 0FFFFH.
When the EPROM programming feature in MCS BASIC-52 is used, BASIC assumes that the EPROM to be programmed is addressed starting at location 8000H. MCS BASIC-52 can only program EPROMS addressed between 8000H and 0FFFFH. When the PROG command is used for the first time, on an erased EPROM, MCS BASIC-52 stores this program beginning at address 8010H. Locations 8000H through 800FH are used to save the baud rate information, plus configuration information. Some suggestions for implementation of the RAM/EPROM mode are shown in figure 2A and figure 2B.
10.2 EPROM PROGRAMMING CONFIGURATION/TIMING
With the proper hardware, the MCS BASIC-52 device can program just about any EPROM or EEPROM device. The only requirement for EPROM programming is that the EPROM to be programmed is addressed starting at location 8000H. MCS BASIC-52 requires very little external hardware to program EPROMS. All of the critical EPROM programming timings are generated by three I/O port pins on the MCS BASIC-52 device. These pins provide the following signals:
PORT 1, BIT 3 (pin 4 on the 8052AH) is used to DISABLE the ALE signal to the extemal latched required by the 8052AH when extemal memory is addressed. This pin should be logically ANDED with ALE. A simple TTL gate, such as a 74LS08 can be used to perfomm the ANDING function. Under normal operation, P1.3 is in a logical high state (1). ONLY DURING EPROM PROGRAMMING IS P1.3 PLACED IN A LOGICAL LOW STATE (0). Disabling the ALE signal to the extemal latch is required to program EPROMS because of the way MCS BASIC-52 carries out the EPROM programming process.
During programming, MCS BASIC-52 treats I/O PORT 0 and I/O PORT 2 as I/O ports, not as address/ data ports. MCS BASIC-52 first writes the low order address to be programmed to PORT 0. The data in PORT 0 is then latched into the external address latch and then MCS BASIC-52 disables the ALE signal to the latch by clearing bit P1.3. Thus, the low order address is "pemmanently" stored in the external latch. MCS BASIC-52 then writes the high order address to PORT 2 and the DATA to be programmed to PORT 0. So, the extemal address latch contains the low order address, PORT 2 contains the high order address, and PORT 0 contains the DATA when EPROM programming occurs.
When PORT 0 on the 8052AH is used as an I/O port, the output structure is an "open drain" configuration. This requires that "pull-up" resistors be placed on PORT 0 to permit MCS B ASIC-52 to program EPROMS. Experimentally, 10K ohm pull-ups resistors on PORT 0 have yielded satisfactory results.
In Version 1.1, INT0 must be kept high when programming EPROMs.
P1.4--PROGRAM PULSE WIDTH
PORT 1, BIT 4 (pin 5 on the 8052AH) is used to provide the 50 millisecond or the 1 millisecond programming pulse. The length of the programming pulse is determined by whether the "normal" or the "INTELligent" EPROM programming mode is selected. MCS BASIC-52 calculates the length of the programming pulse from the assigned crystal value. So, be sure the proper XTAL has been assigned. The accuracy of this pulse is within 10 CPU clock cycles. This pin is normally in a logical high (1) state. It is asserted low (0) to program the EPROMS. Depending on the EPROM to be programmed this signal will be used in different ways. More about this later.
P1.5--ENABLE PROGRAM VOLTAGE
PORT 1, BIT 5 (pin 6 on the 8052AH) is used to enable the EPROM programming voltage. This pin is normally in a logical high (1) state. Prior to the EPROM programming operation, this pin is brought to a logical low (0) state. This pin is used to turn on or off the high voltage (12.5 volts to 25 volts, depending on the EPROM) required to program the EPROMS.
The timing for the EPROM programming pins is shown in figure 3A and figure 3B. The hardware required to program different devices is shown in figure 4. Note that with very little extemal hardware the MCS BASIC-52 device can program virtually all commercially available EPROMS. Additionally, figure 5 suggests a circuit using an INTEL 2816A EEPROM. This circuit also features a push button erase option.
MCS BASIC-52 calculates the programming pulse width when the XTAL value is assigned. To insure proper programming, make sure XTAL is assigned the proper value. MCS BASIC-52 performs the pro- gramming pulse width calculation to within 5 clock cycles, so the accuracy of the programming pulse is well within the limits of any EPROM device.
10.3 SERIAL PORT IMPLEMENTATION
The serial port I/O signals on the 8052AH are TTL compatible signals. They are typically not compatible with most terminals. Figure 6 suggests hardware options for making the serial interface compatible with terminals. The serial port is initialized by MCS BASIC-52 to the 8-bit uart mode. In this mode 8 data bits, plus one start and one stop bit are transmitted. Parity is not used.
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